Phase-changeable devices typically utilize a phase-changeable material layer that changes crystalline structure based on heat provided thereto in the form of an applied current. More particularly, the phase-changeable material layer may be changed into amorphous state when heated and cooled to a temperature close to the melting point of the material. In contrast, when heated and cooled to a temperature lower than the melting point and higher than a crystallization temperature, the phase-changeable material layer may be changed into crystalline state. Typically, the resistivity of the phase-changeable material layer in the amorphous state is higher than that of phase-changeable material layer in the crystalline state. Accordingly, it may be possible to determine whether information stored at the phase-changeable memory cell is a logical “1” or “0” based on the resistance of the phase-changeable material. Germanium (Ge), tellurium (Te), and a material layer containing stibium (Sb) (hereinafter referred to as a “GST” layer) has been widely used as the phase-changeable material layer.
A method of fabricating a data storage element is disclosed in U.S. Pat. No. 6,117,720 to Harshfield entitled “METHOD OF MAKING AN INTEGRATED CIRCUIT ELECTRODE HAVING A REDUCED CONTACT AREA”.
FIG. 1 is a cross-sectional view illustrating a data storage element in a conventional phase-changeable memory device.
The conventional phase-changeable memory device includes an electric conductor 24b, an interlayer insulating layer 32 formed on the electric conductor 24b, and a contact hole formed in the interlayer insulating layer 32. A base layer 40 is formed beneath the contact hole, and a cylindrically shaped spacer 42 is formed on inner sidewalls of the contact hole on the base layer 40. A contact layer 44 connected to the base portion 40 is formed in the cylindrically shaped spacer 42. The contact layer 44 may be a conductive plug. A phase-changeable material layer 46 connected to the conductive plug 44 is formed on the interlayer insulating layer 32.
A memory cell in a phase-changeable memory device may be similar to that of DRAM devices in that the data storage element may be constructed of capacitors. In contrast, however, the data storage element of the phase-changeable memory device may include a phase-changeable material layer. An upper electrode may be formed on the phase-changeable material layer. The upper electrode may be formed of a relatively soft metal such as titanium (Ti) (to promote adhesion) or titanium nitride (TiN) (to suppress heat). Therefore, it may be difficult to prevent etch damage to the upper electrode when a contact pattern is formed to connect the upper electrode and a common electrode.
In addition, a semiconductor device fabrication process may include an alignment step in order to properly align upper and lower patterns. As such, an alignment key may be formed in a scribe line of a wafer. The alignment key may provide alignment between a contact hole (exposing the upper electrode) and the common electrode to be connected to the upper electrode through the contact hole, and may be formed simultaneously when forming the contact pattern.
FIG. 2 illustrates a conventional alignment key which may provide alignment between an upper electrode contact pattern of the phase-changeable memory device and an interconnection layer. FIGS. 3 and 4 are cross-sectional views illustrating conventional methods used to form the alignment key which may provide alignment between the upper electrode contact pattern of the phase-changeable memory device and the interconnection layer.
Referring now to FIG. 2, a memory cell of phase-changeable memory device includes a device isolation layer 12 defining an active region on a substrate 10 and a gate electrode 14 formed on the active region in a cell region B. A first interlayer insulating layer 18 is formed on the surface of the substrate 10 including the gate electrode 14. Conductive plugs 20 are formed on source/drain regions 16. The conductive plugs extend through the first interlayer insulating layer to the source/drain regions 16 at both sides of the gate electrode 14. A second interlayer insulating layer 22 including lower interconnection layers 24a and 24b is formed on the first interlayer insulating layer 18. A data storage element 30 electrically connected to the lower interconnections 24a and 24b is formed on an upper portion of the second interlayer insulating layer 22. The data storage element 30 includes a lower electrode 20, a phase-changeable material pattern 46, and an upper electrode 48. A third interlayer insulating layer 32 is formed on the surface of the substrate including the data storage element 30. In addition, an upper electrode contact pattern 34 is formed extending through the third interlayer insulating layer 32 and connected to the upper electrode 48 of the data storage element 30. An upper interconnection layer 36 is connected to the upper electrode contact pattern 34. In order to align the upper interconnection layer 36 and the upper electrode contact pattern 34, an alignment key pattern 38 is formed in an alignment key region A. The alignment key pattern 38 may be formed in the same step where the upper electrode contact pattern 34 is formed. Accordingly, when a conductive layer is patterned to form the upper interconnection layer 36, the upper electrode contact pattern 34 and the upper interconnection layer 36 may be aligned based on alignment between the alignment pattern and a mask pattern.
Referring now to FIG. 3, a third interlayer insulating layer 32 is formed on the surface of the substrate 10 including the data storage element 30. The third interlayer insulating layer 32 is patterned to form an upper electrode contact hole 34h exposing the upper electrode 48 of the data storage element 30. At this time, the third interlayer insulating layer 32 is also patterned to form an alignment key recess 38k in an alignment key region A. The upper electrode may be formed of a relatively soft metal, such as titanium (Ti) (to promote adhesion) or titanium nitride (TiN) (to suppress heat). Accordingly, the etch rate of the third interlayer insulating layer 32 may be controlled so as not to damage the upper electrode 48 during formation of the upper electrode contact hole 34h and the alignment key recess 38k. As a result, a relatively thin alignment key recess 38k is formed. The depth of the alignment key recess 38k may not be sufficient for use in subsequent processing. In addition, although not shown, a contact pattern may be formed to connect an upper interconnection to a peripheral circuit transistor. However, formation of the upper electrode contact hole 34h and a contact hole for the contact pattern may require complex fabrication steps due to different etch thicknesses of the interlayer insulating layer.
Still, referring to FIG. 3, a conductive layer 34a is formed on the surface of the substrate including the alignment key recess 38k and the upper electrode contact hole 34h. As shown in FIG. 3, since the depth of the alignment key recess 38k is relatively shallow, the conductive layer 34a is formed on an upper portion of the alignment key recess 38k with very little step difference relative to portions thereof on the sidewalls of the alignment key recess 38k. 
Referring now to FIG. 4, the conductive layer 34a is etched-back to form an upper electrode contact pattern 34 filling the upper electrode contact hole 34h. An alignment key pattern 34r having a predetermined step difference is also formed. However, since the depth of the alignment key recess 38k is relatively shallow, the step difference of the alignment key pattern 34r may not be clearly-defined.
A metal layer 36a is formed on the surface of the substrate including the alignment key pattern 34 and the upper electrode contact pattern 34. A photoresist pattern used in forming an upper interconnection layer 36 from the metal layer 36a is formed. However, because the step difference of the alignment key pattern 34 may not be sufficiently defined, an optical signal provided by the alignment key may be relatively weak. As a result, misalignment of the upper interconnection layer 36 and the upper electrode contact pattern 34 may occur due to inexact alignment between the photoresist pattern and the substrate. Moreover, when the upper electrode 48 is formed of TiN, the surface of the electrode may be oxidized during a photoresist ashing process after forming an upper electrode contact hole 34h, which may reduce electrical contact between the upper electrode contact pattern 34 and the upper electrode 48.